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1 zl2005 digital-dc? integrated power management and conversion ic description the zl2005 is an innovative mixed-signal power management and conversion ic that combines a com- pact, efficient, synchronous dc/dc buck controller, adaptive drivers and key po wer and thermal manage- ment functions in one ic , providing flexibility and scalability while decreasing board space requirements and design complexity. zilker labs? digital-dc tech- nology enables a unique blend of performance and features not available in either traditional analog or newer digital approaches, r esolving the issues associ- ated with providing mu ltiple, low-voltage power domains on a single pcb. the zl2005 is designed to be a flexible building block for dc power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3 v input to a mul ti-phase supply operating from a 12 v input. the zl2005 eliminates the need for complicated power supp ly managers as well as numerous external discrete components. all operating features can be configured by simple pin-strap selection, resistor selection or through the on-board serial port. the pmbus?-compliant zl2005 uses the smbus? serial interface for com- munication with other digital-dc products or a host controller. figure 1. block diagram features power management ? digital soft start/stop ? precision delay and ramp-up ? power good/enable ? voltage tracking, sequencing and margining ? voltage/current/temperature monitoring ?i 2 c/smbus communication ? output overvoltage and overcurrent protection ? pmbus compliant power conversion ? efficient synchronous buck controller ? 3 v to 14 v input range ? 0.6 v to 5.5 v output range ? 1% output accuracy ? internal 3 a drivers support >30 a power stage ? fast load transient response ? phase interleaving ? rohs compliant (6 x 6 mm) qfn package applications ? servers/storage equipment ? telecom/datacom equipment ? power supplies (memory, dsp, asic, fpga) ? point of load converters figure 2. efficiency vs. load current current sense ldo temp sensor v (0,1) ss (0,1) vtrk mgn vr vdd bst gh sw isena isenb tach power driver xtemp pwm gl i 2 c scl sda salrt sa (0,1) management en pg cfg uvlo dly (0,1) ilim (0,1) fc (0,1) monitor controller v25 sync pgnd sgnd dgnd adc non- volatile memory vtrk vsen caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright intersil americas inc. 2009-2011. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn6848.2 february 23, 2011 n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t z l 2 0 0 6
2 fn6848.2 february 23, 2011 table of contents 1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3 typical application exam ple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 zl2005 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 digital-dc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 power conversion overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 power management overvi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 power conversion functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 internal bias regulat ors and input supply connecti ons. . . . . . . . . . . . . . . . . . . . . . 15 5.2 high-side driver boost circu it. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 soft start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 power good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8 selecting power train com ponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 current limit threshold selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.11 non-linear response se ttings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.12 efficiency optimized driver dead-ti me control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 power management functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 input undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 output overcurrent protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.5 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.6 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.7 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.8 i2c/smbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.9 i2c/smbus device addre ss selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.10 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.12 monitoring via i2c/smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.13 temperature monitoring using the xtemp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.14 fan monitoring using the tach pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.15 device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 zl2005
3 fn6848.2 february 23, 2011 1 electrical characteristics table 1. absolute maximum ratings operating beyond these limits may cause permanent damage to the device. functional operation beyond the recommended operating conditions is not implied. unless otherwise specif ied, all voltages are measured with respect to sgnd. parameter pin(s) value unit dc supply voltage vdd -0.3 to 17 v logic i/o voltage dly(0,1), en, ilim(0,1), mgn, pg, sa(0,1), salrt, scl, sda, ss(0,1), sync, tach, uvlo, v(0,1) -0.3 to 6.5 v analog input voltages isenb, vsen, vtrk, xtemp, -0.3 to 6.5 v isena -1.5 to +30 v mosfet drive reference vr -0.3 to 6.5 v 120 ma logic reference v25 -0.3 to 3 v 120 ma high-side supply voltage bst -0.3 to +30 v high-side drive voltage gh (v sw - 0.3) to (v bst +0.3) v low-side drive voltage gl (pgnd-0.3) to (vr+0.3+pgnd) v boost to switch differential voltage (v bst - v sw ) bst, sw -0.3 to 8 v switch node continuous sw (pgnd-0.3) to 30 v switch node transient (<100 ns) sw (pgnd-5) to 30 v ground voltage differential (v dgnd -v sgnd ), (v pgnd -v sgnd ) dgnd, sgnd, pgnd -0.3 to +0.3 v junction temperature ? -55 to 150 o c storage temperature range ? -55 to 150 o c lead temperature (soldering, 10 s) ?300 o c esd hbm tolerance (100 pf, 1.5 k ) all 2 kv zl2005
4 fn6848.2 february 23, 2011 table 2. recommended operating conditions and thermal information parameter symbol min typ max unit input supply voltage range, v dd v r tied to v dd (figure 9) 3.0 ? 5.5 v v r floating (figure 9) 4.5 ? 14 v output voltage range v out 0.6 5.5 v operating junction temperature range t j -40 ? 125 c junction to ambient thermal impedance 1 ja ?35?c/w junction to case thermal impedance 2 jc ?5?c/w notes: 1. ja is measured in free air with the device mounted on a multi-layer fr4 test boar d and the exposed metal pa d soldered to a low im pedance ground plane using multiple vias. 2. for jc , the ?case? temperature is measured at the center of the exposed metal pad table 3. electrical specifications unless otherwise specified v dd = 12 v, t a = -40 o c to +85 o c. typical values are at t a = 25 o c. parameter condition min 5 typ max 5 unit input and supply characteristics supply current (i dd ) (no load on gh and gl) f sw = 200 khz ? 16 30 ma f sw = 2,000 khz ? 25 50 ma standby supply current (i dd ) en = low no i 2 c/smbus activity ?25ma vr reference voltage (v r ) v dd 6 v i vr < 50 ma 4.5 5.2 5.5 v v25 reference voltage (v 25 ) v r 3 v i v25 < 50 ma 2.25 2.5 2.75 v output characteristics output voltage adjustment range 0.6 ? 5.5 v output voltage setpoint resolution set using resistors ? 10 ? mv set using i 2 c/smbus ? 0.025 ? % of f.s. 1 output voltage accuracy over line, load and temperature -1 ? 1 % vsen input bias current vsen = 5.5 v ? 110 200 a current sense differential input voltage (ground referenced) v isena - v isenb -100 ? 100 mv current sense differential input voltage ( v out referenced) v isena - v isenb -100 ? 100 mv current sense input bias curre nt ground referenced -100 ? 100 a note: 1. percentage of full scale (f.s.) with temperature co mpensation applied current sense input bias current (v out referenced, v out <= 3.6v) isena -1 ? 1 a isenb -100 ? 100 a zl2005
5 fn6848.2 february 23, 2011 soft start delay duration range set using dly pin or resistor 7 ? 200 ms configurable via i 2 c/smbus 0.007 ? 500 s soft start delay duration accuracy ? 6 ? ms soft start ramp duration range set using ss pin or resistor 0 ? 200 ms configurable via i 2 c/smbus 0 ? 200 ms soft start ramp duration accuracy ? 100 ? s logic input/output characteristics logic input bias current en, pg, scl, sda, salrt, tach -10 ? 10 a during configuration restore -1 ? 1 ma mgn input bias current -1 ? 1 ma logic input low threshold (v il )??0.8v logic input open (n/c) multi-mode logic pins ?1.4?v logic input high threshold (v ih ) 2??v logic output low (v ol ) i ol <= 4 ma ??0.4v logic output high (v oh ) i oh > = - 2 ma 2.25 ? ? v oscillator and switch ing characteristics switching frequency range 200 ? 2000 khz switching frequency setpoint accuracy predefined settings (see table 14) -5 ? 5 % maximum pwm duty cycle factory default 95 ? ? % minimum sync pulse width 150 ? ? ns input clock frequency drift tolera nce external clock signal -13 ? 13 % tachometer characteristics tach pulse width 150 ? ? ns tach frequency range 1 ? 500 hz tach accuracy -10 ? 10 % table 3. electrical specifications unless otherwise specified v dd = 12 v, t a = -40 o c to +85 o c. typical values are at t a = 25 o c. (continued) parameter condition min 5 typ max 5 unit zl2005
6 fn6848.2 february 23, 2011 gate drivers high-side driver voltage (v bst - v sw ) ?4.5?v high-side driver peak gate drive current (pull down) (v bst - v sw ) = 4.5 v 2 3 ? a high-side driver pull-up resistance (v bst - v sw ) = 4.5 v, (v bst - v gh ) = 50 mv ?0.82 high-side driver pull-down resistance (v bst - v sw ) = 4.5 v, (v gh - v sw ) = 50 mv ?0.52 low-side driver peak gate drive current (pull-up) v r = 5 v ? 2.5 ? a low-side driver peak gate drive current (pull-down) v r = 5 v ? 1.8 ? a low-side driver pull-up resistance v r = 5 v, (v r - v gl ) = 50 mv ?1.22 low-side driver pull-down resistance v r = 5 v, (v gl - pgnd) = 50 mv ?0.52 switching timing gh rise and fall time (v bst - v sw ) = 4.5 v, c load = 2.2 nf ? 5 20 ns gl rise and fall time v r = 5 v, c load = 2.2 nf ? 5 20 ns tracking vtrk input bias current vtrk = 5.5 v ? 110 200 a vtrk tracking threshold vtrk >= 0.3 v ? 100 + 100 mv table 3. electrical specifications unless otherwise specified v dd = 12 v, t a = -40 o c to +85 o c. typical values are at t a = 25 o c. (continued) parameter condition min 5 typ max 5 unit zl2005
7 fn6848.2 february 23, 2011 fault protection characteristics uvlo threshold range 2.85 ? 16 v uvlo setpoint accuracy -150 ? 150 mv uvlo hysteresis factory default ? 3 ? % configurable via i 2 c/smbus 0 ? 100 % uvlo delay ? ? 2.5 s power good v out low threshold factory default ? 90 ? % v out power good v out high threshold factory default ? 115 ? % v out power good v out hysteresis factory default ? 5 ? % power good delay set using pin-strap or resistor 4 0?200ms configurable via i 2 c/smbus 0 ? 500 s vsen undervoltage threshold factory default 85 ? % v out configurable via i 2 c/smbus 0 ? 110 % v out vsen overvoltage threshold factory default 115 ? % v out configurable via i 2 c/smbus 0 ? 115 % v out vsen undervoltage/overvoltage fault response time factory default ? 16 ? s configurable via i 2 c/smbus 5 ? 60 s current limit setpoint accuracy (v out referenced) ?10? % f.s. 1 current limit setpoint accuracy 2 (ground referenced) |v isena - v isenb |> 12 mv ? 10 ? % f.s. current limit protection delay factory default ? 5 ? sw 3 configurable via i 2 c/smbus 1 ? 32 temperature compensation of current limit protection threshold factory default ? 4400 ? ppm/ c configurable via i 2 c/smbus 100 ? 12700 thermal protection threshold factory default ? 125 ? c configurable via i 2 c/smbus - 40 ? 125 c thermal protection hysteresis ? 15 ? c notes: 1. percentage of full scale (f.s.) with temperature co mpensation applied 2. t a = 0 o c to +85 o c 3. sw = 1/f sw , f sw switching frequency 4. automatically set to same value as soft start ramp time 5. compliance to datasheet limits is assu red by one or more methods: productio n test, characterization and/or design. table 3. electrical specifications unless otherwise specified v dd = 12 v, t a = -40 o c to +85 o c. typical values are at t a = 25 o c. (continued) parameter condition min 5 typ max 5 unit zl2005
8 fn6848.2 february 23, 2011 2 pin descriptions figure 3. pin assignments (top view) table 4. pin descriptions pin label type 1 description 1 dgnd pwr digital ground. connect to low impedance ground plane. 2synci/o, m 2 clock synchronization input. used to set the frequency of the internal switch clock, to sync to an external cl ock or to output internal clock. 3sa0 i, m serial address select pins. used to assi gn unique address for each individual device or to enable certain management features. 4sa1 5ilim0 i, m current limit select. sets the overcurre nt threshold voltage for isena, isenb. 6ilim1 7 scl i/o serial clock. connect to exte rnal host and/or to other zl2005s. 8 sda i/o serial data. connect to extern al host and/or to other zl2005s. 9 salrt o serial alert. connect to external host if desired. 10 fc0 i loop compensation selection pins. 11 fc1 i 12 v0 i, m output voltage selection pins. used to set v out setpoint and v out max. 13 v1 14 uvlo i, m undervoltage lockout selection. sets the minimum value for v dd voltage to enable v out . notes: 1. i = input, o = output, pwr = power or ground, m = multi- mode pin (refer to section 4.4, ?multi-mode pins,? ) 2. the sync pin can be used as a logic pin, a clock input or a clock output. 3. v dd is measured internally and the value is used to modify the pwm loop gain. sa1 ilim0 ilim1 scl sda salrt dgnd sa0 sync 36-pin mlf 6 x 6 mm sw pgnd gl vr isena isenb vdd gh bst en cfg mgn tach xtemp v25 pg dly0 dly1 v1 uvlo ss0 ss1 vtrk vsen fc0 v0 fc1 exposed paddle connect to sgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 zl2005
9 fn6848.2 february 23, 2011 15 ss0 i, m soft start pins. set the output voltage ramp time during turn-on and turn-off. 16 ss1 17 vtrk i tracking sense input. used to track an external voltage source. 18 vsen i output voltage feedback. co nnect to output regulation point. 19 isenb i differential voltage input for current limit. 20 isena i differential voltage input for current limit. high voltage tolerant. 21 vr pwr internal 5v reference used to power internal drivers. 22 gl o low side fet gate drive. 23 pgnd pwr power ground. connect to low impedance ground plane. 24 sw pwr drive train switch node. 25 gh o high-side fet gate drive. 26 bst pwr high-side drive boost voltage. 27 vdd 3 pwr supply voltage. 28 v25 pwr internal 2.5 v reference us ed to power internal circuitry. 29 xtemp i external temperature sensor input. conn ect to external 2n3904 diode connected transistor. 30 tach i tachometer input used to measure fan speed. connect to tach output of external fan. 31 mgn i digital v out margin control 32 cfg i configuration pin. used to control th e switching phase offset, sequencing and other management features. 33 en i enable. active signal enables pwm switching. 34 dly0 i, m softstart delay select. sets the delay fro m when en is asserted until the output voltage starts to ramp. 35 dly1 36 pg o power good output. epad sgnd pwr exposed thermal pad. connect to low impedance ground plane. internal connection to sgnd. table 4. pin descriptions (continued) pin label type 1 description notes: 1. i = input, o = output, pwr = power or ground, m = multi- mode pin (refer to section 4.4, ?multi-mode pins,? ) 2. the sync pin can be used as a logic pin, a clock input or a clock output. 3. v dd is measured internally and the value is used to modify the pwm loop gain. zl2005
10 fn6848.2 february 23, 2011 3 typical application example figure 4. typical application circuit epad zl2005 1 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 36 dgnd sync sa0 sa1 ilim0 ilim1 scl sda salrt fc0 fc1 v0 v1 uvlo ss0 ss1 vrtk vsen vin bst gh sw pgnd gl vr isena isenb pg dly1 dly0 en cfg mgn tach xtemp v25 v in 10 f 4 v c in 3 x 10 f 25 v l out i 2 c/smbus ? power good output c v25 db bat54 cb 1 f 16 v vr qh ql 2.2 h c out 47 f 6.3 v 4.7 f c vr 6.3 v v out rtn sgnd ntmsf4108 si7344 470 f 2.5 v pos-cap 2*220 f 6.3 v 100 m 12v vr notes: 1. conditions: v in = 12 v, v out = 1.8 v, freq = 400 khz, i out = 20 a 2. the i 2 c/smbus requires pullup resistors. please refer to the i 2 c/smbus specifications for more details. zl2005
11 fn6848.2 february 23, 2011 4 zl2005 overview 4.1 digital-dc architecture the zl2005 is an innovative mixed-signal power con- version and power management ic based on zilker labs? patented digital-dc technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. its unique digital pwm loop utilizes an innovative mixed-signal topology to en able precise control of the power conversion process with no software required, resulting in a very flexible device that is also easy to use. an extensive set of power management functions is fully integrated and can be configured using simple pin connections or via the i 2 c/smbus hardware inter- face using standard pmbus commands. the user con- figuration can be saved in an on-chip non-volatile memory (nvm), allowing ultimate flexibility. once enabled, the zl2005 is immediately ready to regulate power and perform power management tasks with no programming required. the zl2005 can be configured by simply conn ecting its pins according to the tables provided in this document. advanced con- figuration options and real-time configuration changes are available via the i 2 c/smbus interface if desired, and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub-regulation circuitry enables single supply operation from any supply between 3v and 14v with no secondary bias supplies needed. zilker labs provides a comp rehensive set of on-line tools and application notes to assist with power supply design and simulation. an evaluation board is also available to help the user become familiar with the device. this board can be evaluated as a stand-alone platform using pin configuration settings. addition- ally, a windows?-based gui is provided to enable full configuration and mon itoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. please refer to www.zilkerlabs.com for access to the most up-to-date documentation and the powerpilot tm simulation tool, or call your local zilker labs? sales office to order an evaluation kit. zl2005
12 fn6848.2 february 23, 2011 4.2 power conversion overview figure 5. zl2005 detailed block diagram the zl2005 operates as a voltage-mode, synchronous buck converter with a selectable, constant frequency pulse width modulator (p wm) control scheme that uses external mosfets, inductor and capacitors to perform power conversion. figure 6 illustrates the basic synchronous buck con- verter topology showing the primary power train com- ponents. this converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. figure 6. synchronous buck converter in its most simple config uration, the zl2005 requires two external n-channel po wer mosfets, one for the top control mosfet (qh) and one for the bottom synchronous mosfet (ql). the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by the following equation: sync gen en pg mgn ilim(0,1) ss(0,1) dly(0,1) v(0,1) vdd power management digital compensator pll d-pwm mosfet drivers nlr adc adc mux communication temp sensor vdd xtemp vsen isena isenb vsen sw bst v out tach sync salrt sda scl sa(0,1) smbus refcn dac input voltage bus + - { adc vtrk gh gl vr ldo vr fc(0,1) v in v out gh gl zl2005 sw vr bst qh ql cb db c out c in l1 d v out v in --------------- - zl2005
13 fn6848.2 february 23, 2011 during time d, qh is on and v in ? v out is applied across the inductor. the current ramps up as shown in figure 7. figure 7. inductor waveform when qh turns off (time 1-d), the current flowing in the inductor must continue to flow from the ground up through ql, during which the current ramps down. since the output capacitor c out exhibits a low imped- ance at the switching frequency, the ac component of the inductor current is f iltered from the output voltage so the load sees nearly a dc voltage. typically, buck converters specify a maximum duty cycle that effectively limits the maximum output volt- age that can be realized fo r a given input voltage. this duty cycle limit ensures th at the low-side mosfet is allowed to turn on for a minimum amount of time dur- ing each switching cycle, which enables the bootstrap capacitor (cb in figure 6) to be charged up and pro- vide adequate gate drive voltage for the high-side mosfet. see section 5.2, ?high-side driver boost circuit,? for more details. in general, the size of components l1 and c out as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, f sw . therefore, the highest efficiency circuit may be real- ized by switching the mosfets at the lowest possible frequency; however, this w ill result in the largest com- ponent size. conversely, th e smallest possible foot- print may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. each user sh ould determine the optimal combination of size and ef ficiency when determining the switching frequency for each application. the block diagram for the zl2005 is illustrated in figure 5. in this circuit, the target output voltage is regulated by connecting the vsen pin directly to the output regulation point. the vsen signal is then com- pared to a reference voltage that has been set to the desired output voltage level by the user. the error sig- nal derived from this comparison is converted to a dig- ital value with a low-resoluti on, analog to digital (a/ d) converter. the digital signa l is applied to an adjust- able digital compensation filter, and the compensated signal is used to derive the appropriate pwm duty cycle for driving the external mosfets in a way that produces the desired output. the zl2005 also incorporates a non-linear response (nlr) loop to reduce th e response time and output deviation in response to a load transient. the zl2005 has an efficiency optimiza tion circuit that continu- ously monitors the power converter?s operating condi- tions and adjusts the turn-on and turn-off timing of the high-side and low-side mosfets to optimize the overall efficiency of the power supply. 4.3 power management overview the zl2005 incorporates a wide range of configurable power management features that are simple to imple- ment with no external co mponents. ad ditionally, the zl2005 includes circuit protection features that con- tinuously safeguard the load from damage due to unexpected system faults . the zl2005 can continu- ously monitor input voltage, output voltage/current, internal temperature, and the temperature of an exter- nal thermal diode. a power go od output signal is pro- vided to enable power-on reset functionality for an external processor. all power management functions can be configured using either simple pin configuration techniques (fig- ure 8) or via the i 2 c/smbus interface. monitoring parameters can be pre-configured to provide alerts for specific conditions. see ap plication note an13 for more details on smbus monitoring. 4.4 multi-mode pins in order to simplify circuit design, the zl2005 incor- porates patented multi-mode pi ns that allow the user to easily configure many aspects of the device without requiring the user to program the ic. most power man- agement features can be configured using these pins. the multi-mode pins can re spond to four different connections as shown in table 5. any combination of connections is allowed among the multi-mode pins. voltage (v) time current (a) v in ? v out 0 -v out 1-d i o il pk il v d zl2005
14 fn6848.2 february 23, 2011 these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an13). figure 8. pin-strap and resistor setting examples pin-strap settings: this is the simplest implementa- tion method, as no external components are required. using this method, each pin can take on one of three possible states: gnd, open, or high. these pins can be connected to the vr or v25 pins for logic high settings, as either pin provides a regulated volt- age greater than 2v. using a single pin, the user can select one of three settings, and using two pins, the user can select one of nine settings. resistor settings: this method allows a greater range of adjustability when connecting a finite valued resis- tor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so that the device can reliably recogni ze the value of resistance connected to the pin while eliminating the errors asso- ciated with the resistor accu racy. a total of 25 unique selections are available using a single resistor. i 2 c/smbus settings: almost any zl2005 function can be configured via the i 2 c/smbus interface using standard pmbus commands . additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or veri- fied via the i 2 c/smbus. see application note an13 for details. table 5. multi-mode pin configuration pin tied to value gnd (logic low) < 0.8 vdc open (n/c) no connection high (logic high) > 2.0 vdc resistor to gnd set by resistor value zl2005
15 fn6848.2 february 23, 2011 5 power conversion functional description 5.1 internal bias re gulators and input supply connections the zl2005 employs two internal low dropout (ldo) regulators to supply bias vo ltages for internal circuitry, allowing it to operate from a single input supply. the internal bias regulators are as follows: vr: the vr ldo provides a regulated 5v bias supply for the mosfet driver circuits. it is powered from the vdd pin and can supply up to 100ma output current. a 4.7 f filter capacitor is required at the vr pin. v25: the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node and can sup- ply up to 50 ma output current. a 10 f filter capacitor is required at the v25 pin. note: the internal bias regu lators are designed for powering internal circuitry only. do not attach exter- nal loads to any of these pins. the multi-mode pins may be connected to the vr or v25 pins for logic high settings. when the input supply (vdd) is higher than 5.5v, the vr pin should not be connected to any other pin. it should only have a filter capacitor attached as shown in figure 9. due to the dropout voltage associated with the vr bias regulator, the vdd pin must be connected to the vr pin for designs operating from a vdd sup- ply from 3.0v to 5.5v. figure 9 illustrates the required connections for both cases. for input supplies between 4.5v and 5.5v, either method can be used. figure 9. input supply connections 5.2 high-side driver boost circuit the gate drive voltage for the upper mosfet driver is generated by a floating bootstrap capacitor, cb (see figure 4). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through diode db. when ql turns off and the upper mosfet (qh) turns on, the sw no de is pulled up to v dd and the voltage on the bst pin is boosted approximately 5v above v in to provide the necessary voltage for the high-side driver. a schottky diode should be used for db to maximize the high-side drive voltage. 5.3 output voltage selection the output voltage may be set to any voltage between 0.6v and 5.5v provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specifica tion. by connecting the v0 and v1 pins to logic hi gh, logic low, or leaving them floating, v out can be set to any of nine standard voltages as shown in table 6. table 6. pin-strap output voltage settings if an output voltage other than those in table 6 is desired, the resistor setting method can be used. using this method, resistors r0 an d r1 are selected to pro- duce a specific voltage between 0.6v and 5.5v in 10 mv steps. resistor r1 provides a coarse setting and r0 a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors in a stan- dard analog implementation (this typically adds 1.4% error using two 1% resistors). v0 low open high v1 low 0.6v 0.8v 1.0v open 1.2v 1.5v 1.8v high 2.5v 3.3v 5.0v zl2005
16 fn6848.2 february 23, 2011 to set v out using resistors, fo llow the steps below to calculate an index value and then use table 7 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1: index1 = 4 x v out 2. round the result down to the nearest whole num- ber. 3. select the value for r1 from table 7 using the index1 rounded value from step 2. 4. calculate index0 using equation index0 = 100 x v out - 25 x index1 ... 5. select the value for r0 from table 7 using index0 from step 4. example: for v out = 1.33v: index1 = 4 x 1.33v = 5.32 (5); from table 7, using index = 5 r1 = 16.2 k index0 = (100 x 1.33v) - (25 x 5) = 8; from table 7; r0 = 21.5 k figure 10. output voltage resistor setting example the output voltage may also be set to any value between 0.6v and 5.5v using the i 2 c/smbus inter- face. see application note an13 for details. 5.4 start-up procedure the zl2005 follows a specific internal start-up proce- dure after power is applied to the vdd pin. table 8 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock must be stable prior to asserting the en pin. the device requires approximately 10-20 ms to check for specific values stored in its internal mem- ory. if the user has stored values in memory, those val- ues will be loaded. the device will then check the status of all multi-mode pins and load the values asso- ciated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requires approximately 6 ms before its output voltage may be allowed to st art its ramp-up process. if a soft start delay period less than 6 ms has been con- figured (using the dly (0,1) pins), the device will default to a 6 ms delay pe riod. if a delay period of 6 ms or higher is configured, the device will wait for the configured delay period befo re starting to ramp its out- put. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time (using the ss (0,1) pins). table 7. resistors for setting output voltage index r0 or r1 index r0 or r1 010 k 13 34.8 k 111 k 14 38.3 k 2 12.1 k 15 42.2 k 3 13.3 k 16 46.4 k 4 14.7 k 17 51.1 k 5 16.2 k 18 56.2 k 6 17.8 k 19 61.9 k 7 19.6 k 20 68.1 k 8 21.5 k 21 75 k 9 23.7 k 22 82.5 k 10 26.1 k 23 90.9 k 11 28.7 k 24 100 k 12 31.6 k v in v out 1.33v gh gl zl2005 sw v0 r0 21.5 k v1 r1 16.2 k zl2005
17 fn6848.2 february 23, 2011 5.5 soft start delay and ramp times in some system applications , it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its nominal value. in addition, the designer ma y wish to precisely set the time required for v out to ramp to its nominal value after the delay period has expired. the zl2005 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods for v out . these features may be used as part of an overall in-rush current management strategy or to precisely control how f ast a load ic is turned on. the soft start delay period begins when the enable pin is asserted and ends when the delay time expires. the soft-start delay period is set using the dly (0,1) pins. the soft start ramp enables a controlled ramp to the nominal v out value that begins once the delay period has timed out. the ramp-up is guaranteed monotonic and its slope may be precisely set by setting the soft- start ramp time using the ss (0,1) pins. the soft start delay and ramp times can be set to stan- dard values according to table 9 and table 10 respec- tively. if the desired soft start delay and ramp times are not one of the values listed in table 8 and table 9, the times can be set to a cust om value by connecting a resistor from the dly0 or ss0 pin to sgnd using the appropriate resistor value from table 11. the value of this resistor is measured upon start-up or restore and will not change if this resistor is varied after power has been applied to the zl2005. see figure 11 for typical connections using resistors. note: do not connect a resistor to the dly1 or ss1 pin. these pins are not utilized for setting soft-start delay and ramp times. conn ecting an external resistor to these pins may cause conflicts with other device set- tings. table 8. zl2005 start-up sequence step # step name description time duration 1 power applied input voltage is applied to the zl2005?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for values st ored in its internal memory. this step is also performed after a restore command. approx 10-20 ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads values configured by multi-mode pins. 4 device ready the device is ready to accept an enable signal. ? 5 pre-ramp delay the device requires approximately 6 ms following an enable signal and prior to ramping its output. additional pre-ramp delay may be configured using the delay pins. approx. 6 ms table 9. soft start delay settings dly0 low open high dly1 low 0 ms 1 reserved open 5 ms 1 10 ms 20 ms high 50 ms 100 ms 200 ms note: 1. when the device is set to 0 ms or 5 ms delay, it will begin its ramp up after the internal circuitry has initialized (approx. 6 ms). table 10. soft start ramp settings ss0 low open high ss1 low 0 ms 1 1 ms 2 ms open 5 ms 10 ms 20 ms high 50 ms 100 ms 200 ms note: 1. when the soft start ramp is set to zero, the device will ramp up as quickly as the internal circuitry an d output load capacitance will allow. zl2005
18 fn6848.2 february 23, 2011 figure 11. dly and ss pin resistor connections the soft start delay and ramp period can be set to cus- tom values via the i 2 c/smbus interface. when the soft start delay is set to 0 ms, the device will begin its ramp up after the internal circuitry has initialized (approx. 6ms). 5.6 power good the zl2005 provides a power good (pg) signal that indicates the output voltage is within a specified toler- ance of its target level and no fault condition exists. by default, the pg pin will assert if the output is within - 10%/+15% of the target voltage these limits may be changed via the i 2 c/smbus interface. see application note an13 for details. a pg delay period is define d as the time from when all conditions within the zl200 5 for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of us ing an external reset con- troller to control external di gital logic. by default, the zl2005 pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 10 ms, the pg delay will be set to 10 ms. the pg delay may be set independen tly of the soft-start ramp using the i 2 c/smbus as described in application note an13. 5.7 switching frequency and pll the zl2005 incorporates an internal phase locked loop (pll) to clock the inte rnal circuitry. the pll can be driven by an internal oscillator or driven from an external clock source connected to the sync pin. when using the internal os cillator, the sync pin can be configured as a clock output for use by other devices. the sync pin is a unique pin that can per- form multiple functions depe nding on how it is config- ured. the cfg pin is used to select the operating mode of the sync pin as shown in table 12. figure 12 illustrates the typical conn ections for each mode. table 11. dly and ss resistor values dly or ss r dly or r ss dly or ss r dly or r ss 0 ms 10 k 110 ms 28.7 k 10 ms 11 k 120 ms 31.6 k 20 ms 1 2.1 k 130 ms 34.8 k 30 ms 13.3 k 140 ms 38.3 k 40 ms 14.7 k 150 ms 42.2 k 50 ms 16.2 k 160 ms 46.4 k 60 ms 17.8 k 170 ms 51.1 k 70 ms 19.6 k 180 ms 56.2 k 80 ms 21.5 k 190 ms 61.9 k 90 ms 23.7 k 200 ms 68.1 k 100 ms 26.1 k zl2005 ss1 ss0 r ss n/c dly0 dly1 r dly n/c table 12. sync pin function selection cfg pin sync pin function low sync is configured as an input open auto detect mode high sync is configured as an output f sw = 400 khz (default) zl2005
19 fn6848.2 february 23, 2011 figure 12. sync pin configurations configuration a: sync output when the sync pin is configured as an output (cfg pin is tied high), the device will operate from its internal oscillator and w ill drive the resulting internal oscillator signal (preset to 400 khz) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this configuration. configuration b: sync input when the sync pin is configured as an input (cfg pin is tied low), the device will automatically check for a clock signal on the sync pin each time en is asserted. the zl2005?s os cillator will then synchro- nize with the rising edge of external clock. the incoming clock signal must be in the range of 200 khz to 2 mhz and must be stable when the enable pin is asserted. the clock signal must also exhibit the nec- essary performance requiremen ts (see table 3). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the zl2005 will turn off the power fets (qh and ql in figure 4) typically within 10 s. users are discouraged from removing an external sync clock while the zl2005 is operating with enable asserted. configuration c: sync auto detect when the sync pin is config ured in auto detect mode (cfg pin is left open), the device will automatically check for a clock signal on the sync pin after enable is asserted. if a clock signal is present, the zl2005?s oscillator will then synchronize the ri sing edge of the external clock. refer to sync input description. if no incoming clock signal is present, the zl2005 will configure the switching fre quency according to the state of the sync pin as listed in table 13. in this mode, the zl2005 will only read the sync pin con- nection during the start-up sequence. changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on. table 13. switching frequency selection if the user wishes to run the zl2005 at a frequency other than those listed in table 13, the switching fre- quency can be set using an external resistor, r sync , connected between sync and sgnd using table 14. zl2005 logic high cfg sync 200 khz ? 2 mhz zl2005 cfg sync 200 khz ? 2 mhz zl2005 n/c cfg sync 200 khz ? 2 mhz a) sync = output b) sync = input zl2005 n/c cfg sync zl2005 r sync n/c cfg sync logic high logic low open c) sync = auto detect or or sync pin setting frequency low 200 khz open 400 khz high 1 mhz resistor see table 14 zl2005
20 fn6848.2 february 23, 2011 the switching frequency can also be set to any value between 200 khz and 2 mhz using the i 2 c/smbus interface. the available frequencies are bounded by the relation f sw = 8 mhz/n, ( with 4<= n <= 40). see application note an13 for de tails on configuring the switching frequency using the i 2 c/smbus interface. if multiple zl2005s are used together, connecting the sync pins together will force all devices to synchro- nize to one another. the cfg pin of one device must have its sync pin set as an output and the remaining devices must have their sync pins set as an input or all devices must be driven by the same external clock source. note: the switching frequency read back using the appropriate pmbus command will differ slightly from the selected value in table 14. the difference is due to hardware quantization. 5.8 selecting power train components the zl2005 is a synchronous buck controller that uses external mosfets, inductor and capacitors to per- form the power conversion process. the proper selec- tion of the external components is critical for optimized performance. zilker labs offers an online circuit design and simulation tool, powerpilot, to assist designers in this task. please visit http://www.zilkerlabs.com to access pow- erpilot. for more detaile d guidelines regarding com- ponent selection, please refer to application note an11. to select the appropriate power stage components for a set of desired performance goals, the power supply requirements listed in table 15 must be known. design trade-offs the design of a switching regulator power stage requires the user to consider trade-offs between cost, size and performance. for example, size can be opti- mized at the expense of efficiency. additionally, cost can be optimized at the expense of size. for a detailed description of circuit trade-offs, refer to application note an11. to start a design, select a switching frequency (f sw ) based on table 16. this fre quency is a starting point and may be adjusted as the design progresses. inductor selection the output inductor selec tion process will include sev- eral trade-offs. a high inductance value will result in a low ripple current (i opp ), which will reduce the output capacitance requirement and produce a low output rip- ple voltage, but may also compromise output transient load performance. therefore, a balance must be table 14. r sync resistor values f sw r sync f sw r sync 200 khz 10 k 571 khz 28.7 k 222 khz 11 k 615 khz 31.6 k 242 khz 12.1 k 667 khz 34.8 k 267 khz 13.3 k 727 khz 38.3 k 296 khz 14.7 k 889 khz 46.4 k 320 khz 16.2 k 1000 khz 51.1 k 364 khz 17.8 k 1143 khz 56.2 k 400 khz 19.6 k 1333 khz 68.1 k 421 khz 21.5 k 1600 khz 82.5 k 471 khz 23.7 k 2000 khz 100 k 533 khz 26.1 k table 15. power supply requirements example parameter range example value input voltage (v in ) 3.0 ? 14.0 v 12 v output voltage (v out ) 0.6 ? 5.0 v 1.2 v output current (i out ) 0 to ~25 a 20 a output voltage ripple (v orip ) < 3% of v out 1% of v out output load step (i ostep )< io50% of i o output load step rate ? 10 a/s allowable output deviation due to load step ? 50 mv maximum pcb temp. 120c 85c desired efficiency ? 85% other considerations various optimize for small size table 16. circuit design considerations frequency range efficiency circuit size 200 ? 400 khz highest larger 400 ? 800 khz moderate smaller 800 khz ? 2 mhz lower smallest zl2005
21 fn6848.2 february 23, 2011 struck between output ripp le and optimal load tran- sient performance. a good st arting point is to select the output inductor ripple current (i opp ) equal to the expected load transi ent step magnitude (i ostep ): now the output inductance ca n be calculated using the following equation: where v inm is the maximum input voltage. the average inductor current is equal to the maximum output current. the peak inductor current (il pk ) is cal- culated using the following equation where i out is the maximum output current: select an inductor rated for the average dc current with a peak current rating above the peak current com- puted above. in over-current or short-ci rcuit conditions, the inductor may have currents greater than 2x the normal maxi- mum rated output current. it is desirable to use an inductor that is not saturate d at these conditions to pro- tect the load and the po wer supply mosfets from damaging currents. once an inductor is select ed, the dcr and core losses in the inductor are calculated. use the dcr specified in the inductor manufacturer?s datasheet. i lrms is given by: where i out is the maximum output current. next, cal- culate the core loss of the selected inductor. since this calculation is specific to each inductor and manufac- turer, refer to the chosen in ductor?s datasheet. add the core loss and the dcr loss and compare the total loss to the maximum power di ssipation recommendation in the inductor datasheet. output capacitor selection several trade-offs also must be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during tran- sient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capaci- tors, also have relativel y low capacitance values. many designs can use a combination of high capaci- tance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up to the new steady state output current value. as a starting point, allocate one-half of the output volt- age ripple to the capacitor esr and the other half to its capacitance, as shown in the following equations: use these values to make an initial capacitor selection, using a single capacitor or several capacitors in paral- lel. after a capacitor has been selected, the resulting out- put voltage ripple can be calculated using the follow- ing equation: because each part of this equation was made to be less than or equal to half of th e allowed output ripple volt- age, the v orip should be less than the desired maximum output ripple. (3) ostep opp i i = (4) ( ) opp sw v v out out i f v l inm out ? = 1 (5) 2 opp i out pk i il + = 2 lrms ldcr i dcr p = (6) (7) 12 2 2 opp i out lrms i i + = 2 8 orip v sw opp out f i c = (8) (9) opp orip i v esr = 2 (10) out sw opp opp orip c f i esr i v + = 8 zl2005
22 fn6848.2 february 23, 2011 for more information on th e performance of the power supply in response to a tran sient load, refer to applica- tion note an11. input capacitor it is highly recommended th at dedicated input capaci- tors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5 or 12 v ?bulk? supply. this is because of the high rms ripple current that is drawn by th e buck converter topology. this input ripple (i cinrms ) can be determined from the following equation: please refer to applicatio n note an11 for detailed derivation including efficiency and ripple current. without capacitive filtering near the power supply input circuit, this current would flow through the sup- ply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated above to avoid overheating of the capacito rs due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the maximum expect ed input voltage are rec- ommended. bootstrap circuit component selection the high-side driver boost circuit utilizes an external schottky diode (db) and an external bootstrap capaci- tor (cb) to supply sufficie nt gate drive for the high- side mosfet driver. db should be a 20 ma, 30 v schottky diode or equivalent device and cb should be a 1 f ceramic type rated for at least 6.3v. ql selection the bottom mosfet should be selected primarily based on the device?s r ds(on) and secondarily based on its gate charge. to ch oose ql, use the following equation and allow 2?5% of the output power to be dissipated in the r ds(on) of ql (lower output voltages and higher step-down ratios will be closer to 5%): calculate the rms current in ql as follows: calculate the desired maximum r ds(on) as follows: note that the r ds(on) given in the manufacturer?s datasheet is measured at 25c. the actual r ds(on) in the end-use application will be much higher. for example, a vishay si7114 mosfet with a junction temperature of 125c has an r ds(on) 1.4 times higher than the value at 25c. select a candidate mosfet, and calculate the required gate drive current as follows: (15) keep in mind that the tota l allowed gate drive current for both qh and ql is 80 ma. mosfets with lower r ds(on) tend to have higher gate charge requirements, which increases the current and resulting power required to turn them on and off. since the mosfet gate drive circuits are integrated in the zl2005, this power is dissipated in the zl2005 according to the following equation: qh selection in addition to the r ds(on) loss and gate charge loss, qh also has switching loss. the procedure to select qh is similar to the procedure for ql. first, assign 2? 5% of the output power to be dissipated in the r ds(on) of qh using the equation for ql above. as was done with ql, calculate the rms current as follows: calculate a starting r ds(on) as follows, in this exam- ple using 5%: select a mosfet and calculate the resulting gate drive current. verify that th e combined gate drive cur- rent from ql and qh does not exceed 80 ma. (11) () d d i i out cinrms ? = 1 out out ql i v p = 05 . 0 (12) (13) d i i lrms botrms ? = 1 (14) r ds(on) = p ql /i botrms 2 g sw g q f i = (16) inm g sw ql v q f p = (17) d i i lrms toprms = (18) out out qh i v p = 05 . 0 (19) r ds(on) = p qh / i toprms 2 zl2005
23 fn6848.2 february 23, 2011 next, calculate the switching time using where q g is the gate charge of the selected qh and i gdr is the peak gate drive current available from the zl2005. although the zl2005 has a typical gate drive current of 3 a, use the minimum guaranteed current of 2 a for a conservative design. usin g the calculated switching time, calculate the switching power loss in qh using the total power dissipated by qh is given by the fol- lowing equation: (22) mosfet thermal check once the power dissipations for qh and ql have been calculated, the mosfets junction temperature can be estimated. using the junction-to-case thermal resis- tance (r th ) given in the mosfet manufacturer?s data- sheet and the expected maximum printed circuit board temperature, calculate the junction temperature as fol- lows: for further details of thermal analysis and design see application note an10. current sensing components once the current sense me thod has been selected (refer to section 5.9, ?current limit threshold selec- tion,? ), the procedure to select the component is the following: when using the inductor dcr sensing method, the user must also select an r/c network comprised of r1 and cl (see figure 13). figure 13. dcr current sensing these components should be selected according to the following equation: rc = l / dcr -------------------------- (24) r1 should be in the range of 500 to 5 k in order to minimize the power dissip ation through it. the user should make sure the resistor package size is appropri- ate for the power dissipated. once r1 has been calcu- lated, the value of r2 should be selected based on the following equation: r2 = 5 x r1 ----------------------------- (25) if r ds(on) is being used the external low side mos- fet will act as the sensing element as indicated in figure 14. 5.9 current limit threshold selection it is recommended that the user include a current limit- ing mechanism in their desi gn to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload con- dition is imposed on the output. current limiting is accomplished by sensing the current flowing through the circuit during a portion of the duty cycle. output current sensing can be accomplished by mea- suring the voltage across a series resistive sensing ele- ment according to equation 26. v lim = i lim x r sense ---------- ------- (26) where: i lim is the desired maximum current that should flow in the circuit r sense is the resistance of the sensing element v lim is the voltage across the sensing element at the point the circuit shou ld start limiting the out- put current. gdr g sw i q t = (20) (21) sw out sw inm swtop f i t v p = swtop qh qhtot p p p + = (23) th q pcb j r p t t + = max gh gl isena zl2005 isenb sw v in cl v out r1 r2 zl2005
24 fn6848.2 february 23, 2011 the zl2005 supports ?lossless? current sensing, by measuring the voltage across a resistive element that is already present in the circuit. this eliminates addi- tional efficiency losses incurred by devices that must use an additional series resistance in the circuit. to set the current limit thresh old, the user must first select a current sensing method. the zl2005 incorpo- rates two methods for current sensing, synchronous mosfet r ds(on) sensing and inductor dc resistance (dcr) sensing; figure 14 shows a simplified sche- matic for each method. figure 14. current sensing methods the current sensing method can be selected using the ilim1 pin using table 17. the ilim0 pin must have a finite resistor connected to ground in order for table 17 to be valid. if no resistor is connected between ilim0 and ground, the default method is mosfet r ds(on) sensing. the current sensing method can be modified via the i 2 c/smbus interface. please refer to applicatio n note an13 for details . in addition to sele cting the current sensing method, the zl2005 gives the power supply designer several choices for the fault response during over or under current condition. the user can select the number of violations allowed before declaring fault, a blanking time and the action taken when a fault is detected. the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing).it is a configurable parameter. table 17 includes default pa rameters for the number of violations and the blanking time using pin-strap. v in v out gh gl isena zl2005 isenb sw inductor dcr sensing v in v out gh gl isena zl2005 isenb sw mosfet r ds,on sensing table 17. current sensing method selection ilim0 pin 1 ilim1 pin current limiting configuration number of violations allowed 2 comments r ilim0 low ground-referenced (r ds,on ) sensing blanking time: 672 ns 4 best for low duty cycle and low f sw r ilim0 open output-referenced, do wn-slope sensing (inductor dcr sensing) blanking time: 352 ns 4 best for low duty cycle and high f sw r ilim0 high output-referenced, up-slope sensing (inductor dcr sensing) blanking time: 352 ns 4 best for high duty cycle resistor depends on resistor value used; see table 18 notes: 1. 10 k < r ilim0 < 100 k 2. the number of violations allowed prior to issuing a fault response. zl2005
25 fn6848.2 february 23, 2011 table 18. resistor configured current sensing method selection r ilim1 current sensing method number of violations allowed 1 10 k ground-referenced (r ds,on ) sensing best for low duty cycle and low f sw blanking time: 672 ns 1 11 k 3 12.1 k 5 13.3 k 7 14.7 k 9 16.2 k 11 17.8 k 13 19.6 k 15 21.5 k output-referenced, down-slope sensing (inductor dcr sensing) best for low duty cycle and high f sw blanking time: 352 ns 1 23.7 k 3 26.1 k 5 28.7 k 7 31.6 k 9 34.8 k 11 38.3 k 13 42.2 k 15 46.4 k output-referenced, up-slope se nsing (inductor dcr sensing) best for high duty cycle blanking time: 352 ns 1 51.1 k 3 56.2 k 5 61.9 k 7 68.1 k 9 75 k 11 82.5 k 13 90.9 k 15 notes: 1. the number of violations allowed prior to issuing a fault response. zl2005
26 fn6848.2 february 23, 2011 once the sensing method h as been selected, the user must select the voltage threshold (v lim ) based on equation 26, the desired cu rrent limit threshold, and the resistance of the sensing element. the current limit threshold can be selected by simply connecting the ilim0 and ilim1 pins as shown in table 19. the ground-referenced sensing method is being used in this mode. the threshold voltage can also be selected in 5 mv increments by connecting a resistor, r lim0 , between the ilim0 pin and ground according to table 20. this method is preferred if the user does not desire to use or does not have access to the i 2 c/smbus interface and the desired threshold value is contained in table 20. the current limit threshold can be set via the i 2 c/ smbus interface. please refer to application note an13 for further details on setting current limit parameters. 5.10 loop compensation the zl2005 operates as a voltage-mode synchronous buck controller with a fi xed frequency pwm scheme. although the zl2005 uses a digital control loop, it operates much like a traditional analog pwm control- ler. see figure 15 for a simplified block diagram of the zl2005 control loop, which differs from an analog control loop by the consta nts in the pwm and com- pensation blocks. as in the analog controller case, the compensation block compares the output voltage to the desired voltage reference and compensation zeros are added to keep the loop stable. the resulting inte- grated error signal is used to drive the pwm logic, converting the error signal into a duty cycle value to drive the external mosfets. figure 15. control loop block diagram in the zl2005, the compensa tion zeros are set by con- figuring the fc0 and fc1 pins or via the i 2 c/smbus interface once the user has ca lculated the required set- tings. this method eliminates the inaccuracies due to the component tolerances ass ociated with using exter- nal resistors and capacitors. most applications can be served by using the pin- strap compen sation settings listed in table 21. these se ttings will yield a conserva- tive crossover frequency at a fixed fraction of the switching frequency (f sw /20) and 60 of phase margin. table 19. current limit threshold voltage settings ilim0 low open high ilim1 low 20 mv 30 mv 40 mv open 50 mv 60 mv 70 mv high 80 mv 90 mv 100 mv table 20. current limit threshold voltage settings v lim r lim0 v lim r lim0 0 mv 10 k 55 mv 28.7 k 5 mv 11 k 60 mv 31.6 k 10 mv 12.1 k 65 mv 34.8 k 15 mv 13.3 k 70 mv 38.3 k 20 mv 14.7 k 75 mv 42.2 k 25 mv 16.2 k 80 mv 46.4 k 30 mv 17.8 k 85 mv 51.1 k 35 mv 19.6 k 90 mv 56.2 k 40 mv 21.5 k 95 mv 61.9 k 45 mv 23.7 k 100 mv 68.1 k 50 mv 26.1 k d 1-d v in v out l c dpwm r c compensation r o zl2005
27 fn6848.2 february 23, 2011 table 21. pin-strap setting for loop compensation step 1 : using the following equation, calculate the resonant frequency of the lc filter, f n . step 2 : based on table 21, determine the fc0 setting. step 3 : calculate the esr zero frequency (f zesr ). step 4 : based on table 21, determine the fc1 setting. the parameters of the feedback compensation can also be set using the i 2 c/smbus interface. refer to appli- cation note an13 for details. refer to application note an16 for details on setting fc0 and fc1. the zilker labs web site ( www.zilkerlabs.com ) pro- vides an on-line tool (powerpilot) which computes compensation coefficients, and provides a parameter- driven design tool, schematic and bom generation, and circuit simulation includ ing control loop simula- tion. 5.11 non-linear response settings the zl2005 incorporates a non-linear response (nlr) loop that decreases the r esponse time and the output voltage deviation in the even t of a sudden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output be gins to transition outside of the standard regulation limits. this scheme results in a higher equivalent loop bandwidth than is possible using a traditional linear loop. when a load current step function imposed on the out- put causes the output voltage to drop below the lower regulation limit, the nlr ci rcuitry will force a positive correction signal that will turn on the upper mosfet and quickly force the output to increase. conversely, a negative load step (i.e., removing a large load current) will cause the nlr circuitr y to force a negative cor- rection signal that will turn on the lower mosfet and quickly force the output to decrease. the zl2005 has been pre-configured with appropriate nlr settings that correspond to the loop compensa- tion settings in table 21. fc0 range fc0 pin fc1 range fc1 pin f sw /60 < f n < f sw /30 high f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open tbd low f sw /120 < f n < f sw /60 open f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open tbd low f sw /240 < f n < f sw /120 low f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open tbd low f n 1 2 lc ------------- ----------- = (27) f zesr 1 2 crc ----------------- - = (28) zl2005
28 fn6848.2 february 23, 2011 5.12 efficiency optimized driver dead- time control the zl2005 utilizes a closed loop algorithm to opti- mize the dead-time applied between the gate drive sig- nals for the top and bottom fets. in a synchronous buck converter, the mosfet drive circuitry must be designed such that the top and bottom mosfets are never in the conducting stat e at the same time. (poten- tially damaging currents flow in the circuit if both top and bottom mosfets are simultaneously on for peri- ods of time exceeding a few nanoseconds.) con- versely, long periods of time in which both mosfets are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. it is therefore advantageous to minimize this dead- time to provide optimum circuit efficiency. in the first order model of a buck converter, the duty cycle is determined by the equation: d=v out /v in -------------------- (29) however, non-idealities exist that cause the real duty cycle to extend beyond the ideal. deadtime is one of those non-idealities that can be manipulated to improve efficiency. the zl2005 has an internal algo- rithm that constantly adju sts deadtime non-overlap to minimize duty cycle, thus maximizing efficiency. this circuit will null out deadtime differences due to com- ponent variation, temper ature and loading effects. this algorithm is independ ent of application circuit parameters such as mosfet type, gate driver delays, rise and fall times and circuit layout. in addition, it does not require drive or mosfet voltage or current waveform measurements. zl2005
29 fn6848.2 february 23, 2011 6 power management functional description 6.1 input undervolta ge lockout (uvlo) the input undervoltage lock out (uvlo) prevents the zl2005 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85 v and 16 v using the uvlo pin. the simplest implem entation is to connect the uvlo pin as shown in table 22. if the uvlo pin is left unconnected, the uvlo threshold will default to 4.5 v. if the desired uvlo threshold is not one of the listed choices, the user can configure a threshold between 2.85 v and 16 v by connecting a resistor between the uvlo pin and gnd by selecting the appropriate resistor from table 23. v uvlo can also be set to any value between 2.85 v and 16 v via i 2 c/smbus. once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay time, fol- lowed by shutdown if the fault still persists at the end of the delay period. the device will remain in shutdown until permitted to restart. 3. initiate an immediate s hutdown until the fault has been cleared. the user can select a specific num- ber of retry attempts. the default response from a uvlo fault is an imme- diate shutdown of the devi ce. the device will continu- ously check for the presence of the fault condition. if the fault condition is no longer present, the zl2005 will be re-enabled. please refer to application note an13 for details on how to configure the uvlo threshold or to select spe- cific uvlo fault response options via the i 2 c/smbus interface. 6.2 output overvoltage protection the zl2005 offers an internal output overvoltage pro- tection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. this feature is especially useful in protecting expensive processors, fpgas, and asics from excessive voltages. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15 % higher than the target output voltage by default. if the voltage at the vsen pin exceeds this upper threshold level, the pg pin will de-assert. the device can then respond in a number of ways as fol- lows: 1. initiate an immediate shutdown until the fault has been cleared. the user can select a specific num- ber of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an overvoltage fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condi- tion. if the fault condition is no longer present, the zl2005 will be re-enabled. please refer to application note an13 for details on how to select specific overvoltage fault response options via the i 2 c/smbus interface. table 22. uvlo threshold settings pin setting uvlo threshold low 3 v open 4.5 v high 10.8 v table 23. uvlo resistor values uvlo r uvlo uvlo r uvlo 2.85 v 17.8 k 7.42 v 46.4 k 3.14 v 19.6 k 8.18 v 51.1 k 3.44 v 21.5 k 8.99 v 56.2 k 3.79 v 23.7 k 9.9 v 61.9 k 4.18 v 26.1 k 10.9 v 68.1 k 4.59 v 28.7 k 12 v 75 k 5.06 v 31.6 k 13.2 v 82.5 k 5.57 v 34.8 k 14.54 v 90.9 k 6.13 v 38.3 k 16 v 100 k 6.75 v 42.2 k zl2005
30 fn6848.2 february 23, 2011 6.3 output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s c ontrol ic is enabled. cer- tain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. the zl2005 provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than the target voltage exists after the pre-conf igured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both dr ivers are enabled. the out- put voltage is then ramped to the final regulation value at the ramp rate set by th e ss (0,1) pins. the actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time. see figure 16. i figure 16. output response to pre-bias voltages if the pre-bias voltage is higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre-bias voltage. once the pre-configured soft-start ramp period has expired, the power good pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured out- put voltage. if a pre-bias voltage higher than the overvoltage limit, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. in this case, the device will respon d based on the output over- voltage fault response method that has been selected. see section 6.2, ?output overvoltage protection,? for response options due to an overvoltage condition. 6.4 output overcurrent protection the zl2005 can protect the power supply from dam- age if the output is shorted to ground or if an overload condition is imposed on the output. once the current limit threshold has been selected (see section 5.9, ?current limit threshold selection,? ), the user may determine the desired course of action to be taken when an overload condition exists. the following overcurrent protection response options are available: 1. initiate a shutdown and a ttempt to restart an infi- nite number of times with a preset delay time. 2. initiate a shutdown and attempt to restart the power supply a preset number of times with a pre- set delay between attempts. 3. continue operating throughout a specific delay time, followed by shutdown. 4. continue operating th roughout the fault (this could result in permanen t damage to the power supply). 5. initiate an immediate shutdown. the default response from an overcurrent fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condi- tion. if the fault condition is no longer present, the zl2005 will be re-enabled. ss delay ss ramp target voltage pre-bias voltage v out time ss delay ss ramp target voltage pre-bias voltage v out time v prebias < v target v prebias > v target pg delay zl2005
31 fn6848.2 february 23, 2011 please refer to applicatio n note an15 for details on how to select specific ove rcurrent fault response options via the i 2 c/smbus interface. 6.5 thermal protection the zl2005 includes an on- chip thermal sensor that continuously measures the in ternal temperature of the die and will shut down the device when the tempera- ture exceeds the preset limit. the default temperature limit is set to 125c in the factory, but the user may set the limit to a different valu e if desired. see applica- tion note an13 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to th e device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. initiate a shutdown and attempt to restart an infi- nite number of times with a preset delay time. 2. initiate a shutdown and attempt to restart the power supply a preset number of times with a pre- set delay between attempts. 3. continue operating throughout a specific delay time, followed by shutdown. 4. continue operating throughout the fault (this could result in permanen t damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the temperature. if the temperature has dropped below a value that is approx- imately 15c lower than the selected temperature limit (the over-temperature warn ing threshold), the device will attempt to re-start. if the temperature is still above the over-temperature warning threshold, the device will wait the preset delay period and retry again. the default response from a temperature fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condi- tion. if the fault condition is no longer present, the zl2005 will be re-enabled. please refer to applicatio n note an13 for details on how to select specific temperature fault response options via the i 2 c/smbus interface. 6.6 voltage tracking numerous high performance systems place stringent demands on the order in wh ich the power supply volt- ages are turned on. this is particularly true when powering fpgas, asics, and other advanced proces- sor devices that require multiple supply voltages to power a single die. in most cases, the i/o operates at a higher voltage than the core and therefore the core supply voltage, must not ex ceed the i/o supply voltage by some amount (typically 300 mv). voltage tracking protects these sensitive ics by limit- ing the differential volta ge between multiple power supplies during the power-up and power down sequence. the zl2005 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin w ith no external components required. the vtrk pin is an analog input that, when tracking mode is enable d, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. the zl2005 offers two modes of tracking: 1. coincident. this mode configures the zl2005 to ramp its output voltage at the same rate as the volt- age applied to the vtrk pin. 2. ratiometric. this mode configures the zl2005 to ramp its output voltage at a rate that is a percent- age of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different track- ing ratio. figure 17 illustrates the ty pical connection and the two tracking modes. zl2005
32 fn6848.2 february 23, 2011 figure 17. tracking modes the master zl2005 device in a tracking group is defined as the device that has the highest target output voltage within the group. th is master device will con- trol the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 10 ms must be configured in to the master device using the dly0/1 pins, and the user may also configure a specific ramp rate using the ss0/1 pins. any device that is configured for tracking mode will ignore its soft-start delay and ramp time settings (ss0/1 and dly0/1 pins) and its output will take on the turn-on/ turn-off characteristics of the reference voltage present at the vtrk pin. the tracking mode for all other devices can be set by connecting a resistor from the ss1 pin to ground according to table 24. all of the enable pins in the tracking group must be con- nected together and driven by a single logic source. . v out v out time coincident ratiometric v trk v in v out q1 q2 l1 c1 gh gl sw zl2005 vtrk v trk v out v out time v trk table 24. tracking mode configuration r ss1 tracking ratio upper track limit ramp-up/ramp-down behavior no resistor tracking mode is disabled 10 k 100% limited by target voltage and 110% of v(0,1) pin-strap setting output not allowed to decrease before pg 11 k output will always follow vtrk 12.1 k limited by vtrk pin voltage 110% of v(0,1) pin-strap setting output not allowed to decrease before pg 13.3 k output will always follow vtrk 14.7 k 50% limited by target voltage and 110% of v(0,1) pin-strap setting output not allowed to decrease before pg 16.2 k output will always follow vtrk 17.8 k limited by vtrk pin voltage 110% of v(0,1) pin-strap setting output not allowed to decrease before pg 19.6 k output will always follow vtrk zl2005
33 fn6848.2 february 23, 2011 6.7 voltage margining the zl2005 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its spec ified supply voltage range. the mgn pin is a ttl-compatible input that is con- tinuously monitored and can be driven directly by a processor i/o pin or other logic-level output. the zl2005?s output will be forced higher than its nominal setpoint when the mgn pin is driven high, and the output will be forced lower than its nominal setpoint when the mgn pin is driven low. when the mgn pin is left floating (high impedance), the zl2005?s output voltage will be set to its nominal voltage setpoint determined by the v0 and v1 pins and/or the i 2 c/smbus settings that configure the nom- inal output voltage. de fault margin limits of v nom 5% are pre-loaded in the fa ctory, but the margin lim- its can be modified through the i 2 c/smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage setpoint deter- mined by the v0 and v1 pins. the margin limits and the mgn command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nominal output voltage and either ma rgin limit can be config- ured through the i 2 c/smbus interface. please refer to application note an13 for detailed instructions on modifying the margin ing configurations. 6.8 i 2 c/smbus communications the zl2005 provides an i 2 c/smbus digital interface that enables the user to c onfigure all aspects of the device operation as well as monitor the input and out- put parameters. the zl2005 can be used with any standard 2-wire i 2 c host device. in addition, the device is compatible w ith smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuo us fault monitoring. the zl2005 accepts most standard pmbus commands. 6.9 i 2 c/smbus device address selection when communicating with multiple zl2005s using the i 2 c/smbus serial interface, each device must have its own unique address so the host can distinguish between the devices. the device address can be set according to the pin-strap options listed in table 25 to provide up to eight unique device addresses. address values are right-justified. if additional device addresses are required, a resistor can be connected to the sa0 pin according to table 26 to provide up to 25 unique device addresses. in this case the sa1 pin should be tied to sgnd. if more than 25 unique device addresses are required or if other smbus address values are desired, both the sa0 and sa1 pins can be configured with a resistor to sgnd according to the eq uation (30) and table 27. smbus address = 25 x (sa1 index) + (sa0 index) (30) table 25. serial bus device address selection sa1 low open high sa0 low 0x20 0x23 0x26 open 0x21 0x24 0x27 high 0x22 0x25 reserved table 26. smbus address values smbus address r sa0 smbus address r sa0 0x00 10 k 0x0d 34.8 k 0x01 11 k 0x0e 38.3k 0x02 12.1 k 0x0f 42.2 k 0x03 13.3 k 0x10 46.4 k 0x04 14.7 k 0x11 51.1 k 0x05 16.2 k 0x12 56.2 k 0x06 17.8 k 0x13 61.9 k 0x07 19.6 k 0x14 68.1 k 0x08 21.5 k 0x15 75 k 0x09 23.7 k 0x16 82.5 k 0x0a 26.1 k 0x17 90.9 k 0x0b 28.7 k 0x18 100 k 0x0c 31.6 k zl2005
34 fn6848.2 february 23, 2011 using this method, the user can theoretically configure up to 625 unique smbu s addresses, however the smbus is inherently lim ited to 128 devices so attempting to configure an address higher than 128 will cause the device address to repeat (i.e, attempting to configure a device address of 129 would result in a device address of 1). therefore, the user should use index values 0-4 on the sa1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. 6.10 phase spreading when multiple point of load converters share a com- mon dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance require- ments and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses propor- tional to the i rms 2 are reduced dramatically. in order to enable phase sp reading, all converters must be synchronized to the same switching clock. the cfg pin is used to set the configuration of the sync pin for each device as described in section 5.7, ?switching frequency and pll,? . selecting the phase offset for the device is accom- plished by selecting a device address according to the following equation: phase offset = device address x 45 for example: a device address of 0x00 or 0x20 would config- ure no phase offset a device address of 0x01 or 0x21 would config- ure 45 of phase offset a device address of 0x02 or 0x22 would config- ure 90 of phase offset. the phase offset of each device may also be set to any value between 0 and 337.5 in 22.5 increments via the i 2 c/smbus interface. please refer to application note an13 for details. 6.11 output sequencing a group of zl2005 devices may be configured to power up in a predetermined sequence. this feature is especially useful when po wering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage. multi-device sequencing can be achieved by configuring each device through the i 2 c/ smbus interface or by using zilker labs? patented autonomous sequencing mode. autonomous sequencing mode configures sequencing using status information broadcast by zl2005 onto the i 2 c/smbus pins scl and sda. no i 2 c or smbus host device is involved in this method, but the scl and sda pins must be interconnected between all devices that the user wi shes to sequence using this method. note: pull-up resistors on scl and sda are required and should be se lected using the criteria in the smbus 2.0 specification. the sequence order is determined using each device?s i 2 c/smbus device address. using autonomous sequencing mode (configured using the cfg pin), the devices must exhibit sequential device addresses with no missing addresses in the chain. this mode will also constrain each device to have a phase offset according to its device address as described in section 6.10, ?phase spreading? on this page. table 27. smbus address index values sa0 or sa1 index r sa sa0 or sa1 index r sa 0 10 k 13 34.8 k 111 k 14 38.3 k 212.1 k 15 42.2 k 313.3 k 16 46.4 k 414.7 k 17 51.1 k 516.2 k 18 56.2 k 617.8 k 19 61.9 k 719.6 k 20 68.1 k 821.5 k 21 75 k 923.7 k 22 82.5 k 10 26.1 k 23 90.9 k 11 28.7 k 24 100 k 12 31.6 k zl2005
35 fn6848.2 february 23, 2011 the group will turn on in or der starting with the device with the lowest address an d will continue to turn on each device in the address chain until all devices con- nected have been turned on. when turning off, the device with the highest address will turn off first fol- lowed in reverse order by the other devices in the group. sequencing is configured by connecting a resistor from the cfg pin to ground as described in table 28. the cfg pin is used to set the configuration of the sync pin as well as to determine the sequencing method and order. please refer to switching frequency and pll for more details on the operating parameters of the sync pin. . multiple device sequencing may also be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. this method places less restrictions on device address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its device address. event based sequencing and fault spreading are broad- cast in address groups of up to eight zl2005 devices. an address group consists of all devices whose addresses differ in only the three least significant bits of the address. for exampl e, addresses 20, 25 and 27 are all within the same group. addresses 1f, 20 and 28 are all in different groups. devices in the same address group can broadcast power on and power off sequenc- ing and fault spreading ev ents with each other. devices in different groups cannot. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turnoff of the group. please refer to application note an13 for details on sequencing via the i 2 c/smbus interface. 6.12 monitoring via i 2 c/smbus a system controller can mon itor a wide variety of dif- ferent zl2005 system pa rameters through the i 2 c/ smbus interface. the contro ller can monitor for fault conditions by monitoring the salrt pin, which will be asserted when any number of pre-configured fault or warning conditions occu r. the system controller can also continuously monitor for any number of power conversion parameters including but not limited to the following: 1. input voltage 2. output voltage 3. output current 4. internal junction temperature 5. temperature of an external device 6. switching frequency 7. duty cycle please refer to application note an13 for details on how to monitor specific parameters via the i 2 c/ smbus interface. 6.13 temperature monitoring using the xtemp pin the zl2005 supports measurement of an external device temperature using either a thermal diode inte- grated in a processor, fpga or asic, or using a dis- crete diode-connected npn transistor such as a 2n3904 or equivalent. fi gure 18 illustrates the typical connections required. table 28. cfg pin configurations for sequencing r cfg sync pin config sequencing configuration 10 k input sequencing is disabled 11 k auto detect 12.1 k output 14.7 k input the zl2005 is configured as the first device in a nested sequencing group. turn-on order is based on the device smbus address. 16.2 k auto detect 17.8 k output 21.5 k input the zl2005 is configured as a last device in a nested sequencing group. turn-on order is based on the device smbus address. 23.7 k auto detect 26.1 k output 31.6 k input the zl2005 is configured as the middle device in a nested sequencing group. turn-on order is based on the device smbus address 34.8 k auto detect 38.3 k output zl2005
36 fn6848.2 february 23, 2011 figure 18. external temperature monitoring 6.14 fan monitoring using the tach pin the zl2005 can monitor the tachometer pulse of an external 3-wire fan connected to the tach pin. the device will report a revo lutions per minute (rpm) value assuming one pulse pe r revolution. the tach pin is only monitored when the device is enabled or when it is configured to always be in monitoring mode. refer to applicat ion note an13 for more details on configuring specific operating modes. 6.15 device security features note that the zl2005 integr ates several security mea- sures to ensure that the user can only restore the device to a level that has been ma de available to them. during the initialization process, the zl2005 checks for stored values contained in its internal memory. the zl2005 offers two internal memory storage units that are accessible by the user as follows: 1. default store: a power supply module manufac- turer may want to protec t the module from damage by preventing the user from being able to modify certain values that are related to the physical con- struction of the module. in this case, the module manufacturer would use the default store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory setting. 2. user store: the manufacturer of a piece of equip- ment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manu- facturer would use the user store to achieve this goal. please refer to application note an13 for details on how to set specific security measures via the i 2 c/ smbus interface. zl2005 sgnd xtemp discrete npn 2n3904 zl2005 sgnd xtemp embedded thermal diode p fpga dsp asic zl2005
37 fn6848.2 february 23, 2011 7 package dimensions 1. dimensioning and tolerancing conform to asme y14.5m. ? 1994. 2. all dimensions are in millimeters (mm), o is in degrees. 3. n is the total number of terminals. 4. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. nd and ne refer to the number of terminals on each d and e side, respectively. 6. maximum package warpage is 0.05 mm. 7. maximum allowable burrs is 0.076 mm in all directions. 8. pin #1 id on top will be laser marked. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10. this drawing conforms to jedec registered outline mo-220. notes: zl2005
38 fn6848.2 february 23, 2011 8 ordering information z l 2 0 0 5 a l n f t product designator shipping option t = tape & reel 100 pcs t1 = tape & reel 1000 pcs contact factory for other options lead finish f = lead-free matte tin firmware revision alpha character operating temperature range l = -40 to +85 c package designator a = qfn p acka g e zl2005
39 fn6848.2 february 23, 2011 related documentation the following application support documents and to ols are available to help simplify your design. revision history item description zl2005evk1 evaluation kit: 12v to 3.3v, 20a dc/dc converter with power management an10 application note: zl2 005 and zl2105 thermal and layout guidelines an11 application note: zl2005 component selection guide an13 application note: pmbus command set an15 application note: zl2005 curre nt protection and measurement an16 application note: zl2005 dig ital control loop compensation an21 application note: protecting conf iguration during manufacturing an22 application note: autonomous sequencing technology an23 application note: voltage tracking with the zl2005 revision number description date 1.0 initial release 2/16/06 1.1 table 3 update 4/25/06 1.2 table 3, 28 update 9/07/06 fn6848.0 assigned file number fn6848 to datasheet as this will be the first release with an intersil file nu mber. replaced header and footer with intersil header and footer. updated disclaimer information to read "intersil and it's subsidiaries including zilker labs, inc." no changes to datasheet content 2/18/09 fn6848.0 stamped datasheet ? not recommended for new designs recommended replacement part zl2006 ?. no file rev, no date change, no changes to datasheet content. 8/5/09 fn6848.1 added following statement to disclaimer on page 40: ?this product is subject to a license from power one, inc. related to digital power technology as set fo rth in u.s. patent no. 7,000,125 and other related patents owned by power one, inc. these license rights do not extend to stand- alone pol regulators unless a royalty is paid to power one, inc.? 12/8/10 fn6848.2 in table 3, under ?uvlo setpoint accuracy,? changed min/max limits from -100 / 100 to -150 / 150 mv. in table 3, added note 5: "com pliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." and referenced it in the headings of the min and max columns. 1/20/2011 zl2005
zilker labs, inc. 4301 westbank drive building a-100 austin, tx 78746 tel: 512-382-8300 fax: 512-382-8329 ? 2006, zilker labs, inc. all rights reserved. z ilker labs, digital-dc, au tonomous sequencing and the zilker labs logo are trademarks of zilker labs , inc. all other products or brand names mentioned herein are trademarks of their respective holders. this document contains information on a product under development. specif ications are subject to change without notice. pricing, specifications and availability are subject to change without notice. please see www.zilkerlabs.com for updated information. this product is not intended for use in con- nection with any high-risk activity, including without limitation, air tr avel, life critical medical opera- tions, nuclear facilities or equipment, or the like. the reference designs contained in this document are for reference and ex ample purposes only. the reference designs are provided "as is " and "with all faults" and intersil corporation and it's subsidiaries including zilker labs, inc. disclaims all warranties, whether express or implied. zilker labs shall not be liable for any damages, whether direct, indirect, consequential (including loss of profits), or otherwise, resulting from the reference designs or any use thereof. any use of such reference design s is at your own risk and you agree to indem- nify intersil corporation and it's subsidiaries including zilker la bs, inc. for any damages resulting from such use. this product is subject to a licen se from power one, inc. related to digital power technology as set forth in u.s. patent no. 7,000,125 and other relate d patents owned by power one, inc. these license rights do not extend to stand-alone pol regulato rs unless a royalty is paid to power one, inc. 40 fn6848.2 february 23, 2011 zl2005

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